The technology of programmable logic devices (PLDs) has progressed to a level such that it is possible to implement a microprocessor on a PLD and host an operating system such as Linux. Not only may this support various system on a chip (SOC) applications, but with the capabilities of a PLD such as a Virtex field programmable gate array (FPGA) from Xilinx, the SOC is reconfigurable to suit changing requirements or adjust to changing environmental conditions.
The configuration of a PLD such as an FPGA, generally refers to the state of the configurable logic resources of the device as programmed to accomplish a set of required functions. Data that is loaded into the device to achieve a desired configuration may be referred to as a configuration bitstream or configuration data. The state of the device generally refers to the contents of registers and memories in the device at a chosen time while the device is performing the desired functions.
In developing and maintaining a design it may become necessary to debug the design as implemented in a configured PLD. Devices such as the Virtex FPGA have various modes available for accessing the configuration data and state. For example, for general needs the SelectMap interface of the Virtex FPGA may be used to load a configuration bitstream into the device or read back configuration data from the device. For testing and diagnostic activities, a boundary scan interface may be used to establish or read back state data. The internal configuration access port (ICAP) may be implemented on a Virtex FPGA to manipulate configurable resources after the device has already been configured.
Even though these interfaces for accessing configuration data or device state are suitable for most purposes, the interfaces are low-level (less abstract) and may be unnecessarily complex for some applications. For example, to the developer of an application in which the PLD is to be re-configured while being part of a running system (run-time reconfiguration), the low-level interface may not be familiar. The developer's lack of familiarity may present scheduling, reliability, and cost issues.
In some scenarios it may be desirable to add debug logic to the design undergoing diagnosis. However, debug logic added to a design may inadvertently change the behavior of the system. In addition, PLD resources may be limited, thereby limiting use of debug logic on the device.
The present invention may address one or more of the above issues.